Design of Hybrid Full Adder using 6T-XOR-Cell for High Speed Processor Designs Applications

Hybrid-logic implementation is highly suitable in the design of a full adder circuit to attain high-speed low-power consumption, which helps n any high speed ALUs that can be used varies processors and applicable for IoT- Application. XOR/XNOR-cell, Hybrid Full Adder (HFA) are fundamental building block perform arithmetic operation. In this paper, different types high-speed, 6T-XOR/XNOR-cell designs being proposed simulated results presented. The HFA using cadence virtuoso environment 45nm technology with supply voltage as 0.8V at 1GHz. consumes power 1.555uw, delay 36.692ns. Layout drawn both 6T-XOR/XNOR-cell, 1- bit designs. XOR/XNOR-cells designed based on combination normal CMOS-inverter Pass Transistor Logic (PTL). Which end device such ALU implemented applications?